This application claims the priority benefit of Taiwan application serial no. 90117179, filed Jul. 13, 2001.
1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a metal oxide semiconductor (MOS) device.
2. Description of Related Art
The trend in the development of very large scale integration technology is that as the wafer where the integrated circuit devices are formed becomes larger, the line width of the device becomes narrower. This trend enhances the performance of the integrated circuits while reducing the cost of production. For a metal oxide semiconductor, as the channel length is shortened, the size of the device diminishes, and operation speed of the device increases.
As the device becomes smaller, however, the shortened channel length will create an overlap between the depletion layer of the source/drain and the channel. The overlapping area between the depletion layer of the source/drain and the channel gets larger as the channel length gets shorter, and when the channel length has been shortened substantially this leads to what is known as the xe2x80x9cshort channel effectxe2x80x9d. A common solution for this is to form a lightly doped drain in the device. When the line width of the device is smaller than 0.25 xcexcm, the depth of the lightly doped drain must be persistently reduced, and the speed of the device slows down because of the increased resistance in the lightly doped drain. To avoid these drawbacks, a source/drain extension using a high dosage of dopants has recently been proposed to replace the lightly doped drain. A thermal process must be conducted on wafers having an implanted source/drain extension to repair damaged crystalline lattices of the substrate and to activate the implanted dopants before entry into the subsequent process. However, lateral diffusion of the source/drain extension occurs during the thermal process, so that the junction depth of the extension increases and the short channel effect gets even more serious than before.
In addition, when semiconductor device line width is below 0.25 xcexcm, a high current leakage existing in the source/drain extension caused by the shortening of the channel length cannot be prevented. Therefore, a solution for this fault is proposed in which two implanted pocket regions next to the source/drain extension are formed at the two ends of the channel. A lightly-doped ion implantation is performed to form a source/drain extension in the substrate after a gate has been formed but before forming its spacers. A tilted pocket implantation into the substrate follows to form two pocket regions.
The pocket regions formed according to the method above can effectively block the current leakage that occurs in the channel as line width of the device decreases to 0.25 xcexcm. However, after line width of the device gets below 0.13 xcexcm, what has been termed the xe2x80x9creverse short channel effectxe2x80x9d (RSCE) arises as a result of the close proximity of the two pocket regions formed by the conventional process. When the length of the channel is minimized to a particular extent, the threshold voltage of the device rises so quickly that it causes device breakdown. Moreover, in the prior art, the location of the pocket regions formed in the substrate is relatively deep, therefore their ability to block the drawback caused by the short channel effect is not sufficient.
Therefore, it is an object of the present invention to provide a fabrication method for a metal oxide semiconductor device that can control the junction depth and the implanting profile of the source/drain extension of the device.
It is another object of the present invention to provide a fabrication method for a metal oxide semiconductor device that renders the implanted pocket regions close to the surface of the substrate.
It is a further object of the present invention to provide a fabrication method for a metal oxide semiconductor device that can restrain the short channel effect and reduce the reverse short channel effect to further complete the fabrication of a deep sub-micron device.
The present invention provides a fabrication method for a metal oxide semiconductor device comprising the following steps. First, a substrate is provided, wherein a gate is formed on the substrate and a spacer is formed on the sidewalls of the gate. Subsequently, a source/drain region is formed in the substrate beside the gate. The preceding process further includes a step of forming a self-aligned silicide layer on the exposed surface of the gate and the source/drain region. Subsequently, a portion of the spacer is removed by using an etching process to form a substantially triangular spacer with sharp corners, and then a tilted ion implantation for the substrate is performed to form pocket regions within the substrate beside the gate. By adjusting the energy and the angle of the tilted ion implantation, the location of the pocket regions and the distribution of dopants can be controlled in order to form the pocket regions near the substrate surface. After this, a tilted-angle implantation for the substrate is performed to form a source/drain extension located within the substrate beside the gate and underlying the sharp-corner spacer. Finally, the junction depth and the dopant profile of the source/drain extension are adjusted by using a thermal cycle process.
In addition, in the present invention after formation of the substantially triangular spacer with sharp corners, this method for fabricating a metal oxide semiconductor device further comprises the ability to switch the order of the steps for performing a tilted pocket implantation and for forming a source/drain extension. That is, it is allowable, after formation of the sharp-corner spacer, to perform a tilted-angle implantation into the substrate to form the source/drain extension within the substrate beside the gate and underlying the sharp-corner spacer, and then perform a tilted pocket implantation into the substrate to form the pocket regions within the substrate beside the gate, keeping the order of the other steps the same.
In the present invention, a sharp-corner spacer is used to reduce the implantation depth in the substrate, so that the pocket regions may be located near the surface of the substrate and the interval between the two pocket regions next to the source/drain extension can be increased to prevent the two pocket regions overlapping. Thus, the short channel effect is inhibited and the reverse short channel effect also decreased. Moreover, the sharp-corner spacer is also used to reduce the implantation depth so as to form a relatively shallow source/drain extension within the substrate beside the gate and underlying the spacer. In the present invention, the lateral diffusion effect of the source/drain extension is alleviated and the junction depth of the source/drain extension won""t become too deep due to the thermal process, therefore the short channel effect is restrained. In addition, after a subsequent thermal cycle process, the junction depth and the dopant profile of the source/drain extension can be adjusted more accurately to suppress the short channel effect.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.